The present invention relates to a method and an apparatus which irradiate an electron beam, an ion beam or a similar charged particle beam to an IC under test, measure the amount of a secondary electron emission from the irradiated point, display the potential distribution as a potential contrast image and identify defect portions of the IC.
The following test method is proposed in the page 14 (line 23 and below) of U.S. patent application No. 08/337,230 entitled "METHOD AND APPARATUS FOR FORMING A POTENTIAL DISTRIBUTION IMAGE OF A SEMICONDUCTOR INTEGRATED CIRCUIT" filed on Nov. 7, 1994.
After furnishing test patterns from a test pattern generator to drive the IC, the update of the test pattern is stopped. In this condition, an electron beam is irradiated to an area including the circuit wiring portion where an attention is necessary to obtain a potential contrast image data. A series of above operations are carried out under the conditions that a normal power supply voltage (e.g., 5V) is applied to the IC and an abnormal power supply voltage (e.g., 3-4V) is applied to the IC. Then, the difference image data between the potential contrast image data obtained in the normal power supply voltage and the potential contrast image data obtained in the abnormal power supply voltage is generated and a circuit pattern where the two potential contrast images do not match is identified. Then, a defect portion of the IC is presumed based on the mismatch location and the pattern address at which the test pattern was stopped. In this case, after obtaining a plurality of the difference image data, those data are summed so that the image contrast can be intensified. By this summing process, the portion of the circuit wiring pattern where the contrast image data mismatch is intensified to black or white and can easily be pinpointed.
According to this proposed defect detection method, it is difficult to determine how many test patterns (until which pattern address) should be applied to the IC and it is time consuming to pinpoint the circuit wiring portion on the displayed difference image since the portion displayed on a monitor is only a part of the entire IC surface. Also, when the mismatch wiring portions are found in multiple locations, it is not necessarily appropriate to presume those wiring portions as defect portions. In other word, for example, even if the actual defect is in only one location, the mismatch wiring portions of the difference image are detected in multiple locations in the IC as the test patterns are applied in order. Therefore, it is difficult to determine the actual defect point accurately by observing the multiple difference images.